Reconfigurable circuits have been widely used in the semiconductor industry for field programmable gate arrays (FPGAs) and for the repair of defective memory elements. Moreover, reconfigurable circuits such as FPGAs are also anticipated to play a significant role in the new Three Dimensional Integration (3DI) technology currently under development. 3DI structures typically include multilayer structures that can form a single chip combination with different functionalities. In these multilayer (and multifunctional) systems, reconfigurable circuit connections are needed to provide controllable logic functionality, memory repair, data encryption, as well as other functions.
A programmable via device (PVD) is an enabling technology for high-performance reconfigurable logic applications such as those required for 3DI applications. As the name would suggest, a PVD comprises vias (i.e., vertical contacts) whose resistance can be temporarily or permanently switched (i.e., programmed) between two or more resistance states by applying one or more signals to the device. Recently, the possibility of using phase change materials (PCMs) in PVDs has gained momentum as more is learned about these materials and their integration into integrated circuits. Currently, a ternary alloy of germanium (Ge), antimony (Sb), and tellurium (Te) (GST) (e.g., Ge2Sb2T5) is showing the greatest promise for use in practical PCM-based PVDs, although several other materials are presently under investigation. At room temperature and at moderately elevated temperatures, for example, GST is stable in two phases, a crystalline phase, which is a moderately good conductor of electrical current, and an amorphous phase, which is largely insulating. The GST in a PVD may be converted between these phases by applying a pulse of current (“switching current pulse”) to a heating feature that is located proximate to the GST. This switching current pulse, in turn, acts to resistively heat the heating feature and, as a result, the adjacent GST. A RESET switching current pulse is designed to rapidly heat the GST above its melting point and then to rapidly quench the melted material so that its disordered arrangement of atoms is retained. In this manner, the RESET switching current pulse converts at least a fraction of the GST from a crystalline phase to an amorphous phase. In contrast, a SET switching current pulse is designed to anneal the GST at temperatures below its melting point for a time somewhat longer than the RESET pulse. Such a SET switching pulse converts at least a fraction of the GST from the amorphous phase into the crystalline phase.
Several designs and methods of forming PCM-based PVDs are described in, for example, U.S. Patent Publication No. 2007/0235708 A1, entitled “Programmable via structure for three dimensional integration technology,” and U.S. patent application Ser. No. 11/612,631, entitled “Programmable via structure and method of fabricating same,” which are commonly assigned herewith and are incorporated by reference herein. Nevertheless, despite their promise for use in reconfigurable circuits, there remains a need for refined designs and fabrication techniques for PCM-based PVDs. Ideally such designs and fabrication techniques will be compatible with conventional complimentary-metal-oxide-semiconductor (CMOS) processing.